![](https://s3images.coroflot.com/user_files/individual_files/613050_glcbersqv_ianvijod4gwmaf2.jpg)
Notice that there is no audio artifact during the transitions between the two sine waves. Also the control signals can be seen here as a square pulse.
![](https://s3images.coroflot.com/user_files/individual_files/613050_pvhn89zqeavv7a8ottlojozq0.jpg)
The 1st draft of the schematic which I will be breadboarding and debugging before committing this design to solder. There are no ic's, just discrete components.
![](https://s3images.coroflot.com/user_files/individual_files/613050_nmjho25n4yhlwpvpbgoq3ztwv.jpg)
JFET leads reference will come in handy while building. Gate, Source, Drain.
![](https://s3images.coroflot.com/user_files/individual_files/613050_u_672om_etylzsg0smlfm0al6.png)
JFET cheat sheet which I will often refer to while I work.
![](https://s3images.coroflot.com/user_files/individual_files/613050_8ixk6bblpmpyh48ahibjcdqzm.jpg)
PNP transistors used. Leads reference. Collector, Base, Emitter.
![](https://s3images.coroflot.com/user_files/individual_files/613050_sfdpybk2_athitcqzudg5iq5w.gif)
![](https://s3images.coroflot.com/user_files/individual_files/613050_wthiurhyrxpjabeji048rw6jc.jpg)
NPN transistors used. Leads reference. Collector, Base, Emitter.
![](https://s3images.coroflot.com/user_files/individual_files/613050_jufl9sdqhcwa6an2rrs9bsnv6.jpg)
Initial breadboard build and debug. I had to use 3 x .1 uf capacitors in parallel to come close enough to the .33 uf value in my spice model. Nice trick when exact value caps or resistors are not on hand.
Having some trouble with getting the A to B transition to occur. A Pspice simulation is an ideal case scenario. , Things can behave differently when actual components are utilized to realized the design. Looks like I need to revise the design a little more.
![](https://s3images.coroflot.com/user_files/individual_files/613050_9zyxxtqt62pw4ib9sbh8fy0ck.jpg)
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